High Performance Fractional-N PLL Design and Its Application for 5G New Radio Slides

Abstract: High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, and low power operation. Both analog circuits design and digital calibration techniques will be presented in detail. In addition, a complete LO chain design example for 5G New Radio will be illustrated in a 28/39 GHz dual-polarized 5G mm-wave cellular chipset, supporting 256-QAM and non-contiguous carrier aggregation.