Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures Video

Abstract: Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. To understand the reasons underlying this trend, we develop a behavioral model of resistive IMCs to analyze the signal-to-noise-plus-distortion ratio (SNDR) of MRAM, ReRAM, and FeFET-based IMCs, employing parameter variation and noise models which are validated w.r.t. measured results from a recent MRAM-based IMC prototype in a 22nm process. We obtain fundamental limits on the maximum achievable SNDR under various operating conditions and identify device and circuit parameters that have the most significant impact on the SNDR. Finally, we study the impact of bank level SNDR on network-level accuracy by mapping ResNet-20 (CIFAR-10) to find that MRAM and FeFET-based architectures find it challenging to meet the minimum SNDR required for the classification accuracy to approach that of a fixed-point digital architecture – a result that clearly implies the need for algorithmic and learning-based methods, to improve the inference accuracy of resistive IMC architectures. Next, we hypothesize that the low native SNDR of resistive IMCs might provide resilience against security attacks, such as model extraction attacks (MEAs). This hypothesis is invalidated by employing the behavioral model to develop resistive IMC-specific MEAs,  which are then applied to the 22nm MRAM-based IMC prototype and shown to be quite effective in extracting model weights. The security vulnerability of resistive IMCs is shown to be a function of the SNDR, and the trade-off between energy-accuracy-security of resistive IMCs is quantified. This work opens up opportunities for AI chip designers and security experts to design resistive IMCs that are secure, energy-efficient, and accurate.