Chiplets for AI and Data Centers: Trends and Innovations in I/O Circuit Designs Slides
Yoshinori Nishi
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SSCS
IEEE Members: $11.00
Non-members: $15.00Pages/Slides: 56
Abstract: Today’s complex systems for high-performance computing feature chiplets using advanced packaging technologies, commercially known as EMIB, CoWoS, InFO, FOCoS, and several others from multiple sources. These 2D/2.5D structures require ultra-dense I/O PHYs to deliver a large amount of data between dice over a distance of a few millimeters without adding much power and area penalty to each die.
This talk will highlight several important use cases of chiplets for AI and data centers, and then delve deeper into the latest trends in I/O circuit designs for chiplets. It will also discuss ongoing standardization efforts and I/O circuits for 3D integrations.
Primary Committee:
SSCS