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13 Feb 2021
Abstract: On-chip communication impacts the performance, energy efficiency, and area of systems-on-chip, multi-processors and highly parallel accelerators. This tutorial introduces a range of design options for on-chip interconnects. It presents routing schemes and mapping of different protocol families, flow-control and arbitration, synchronization strategies across clock domains, and fully asynchronous circuits. Finally, it introduces the potential of 3D-chip integration for on-chip communication.
