Basics of Clock-and-Data Recovery Circuits Slides and Transcript

Abstract - The choice of the clock-and-data-recovery (CDR) architecture in serial links dictates many of the block-level circuit specs. In the first half of this tutorial we will discuss the basics of CDR operation, CDR main performance metrics, and the relationship between circuit-level parameters and system-level performance metrics. In the second half, we will review various CDR architectures and their associated design trade-offs. We will conclude with the review of a few practical CDR design considerations.
Bio - Amir Amirkhany is a Director of Engineering at Samsung Display America Lab, San Jose, CA. He received his B.S. from Sharif University of Technology, M.S. from University of California, Los Angeles, and Ph.D. from Stanford University, all in Electrical Engineering. At Samsung Electronics, Dr. Amirkhany is in charge of the development of future generations of high-speed interfaces for Samsung displays. Prior to Samsung, he was an engineering manager at Rambus Inc., where he led the development of DDR and proprietary high-speed memory interfaces. Dr. Amirkhany has authored or co-authored over 25 IEEE conference and journal papers, including a best paper award, and has over 50 issued US patents.