IEEE Members: $8.00
Non-members: $15.00Duration: 11:20
Abstract: With the slowing of Moore's law, computer architects have turned to domain-specific hardware accelerators to improve the performance and efficiency of computing systems. However, programming these systems entails significant modifications to the software stack to properly leverage the specialized hardware. Moreover, the accelerators become obsolete quickly as the applications evolve. What is needed is a structured approach for generating programmable accelerators and for updating the software compiler as the accelerator architecture evolves with the applications. In this talk, I will describe a new agile methodology for co-designing programmable hardware accelerators and compilers. Our methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single specification. This enables faster evolution and optimization of accelerators, because of the availability of a working compiler. I will showcase this methodology using Amber, a coarse-grained programmable accelerator for imaging and machine learning (ML) we designed and fabricated using our flow in TSMC 16 nm technology. I will show how we agilely evolved Amber into Onyx, our next generation accelerator, using an application-driven design space exploration framework called APEX enabled by our hardware-compiler co-design flow.