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01 Mar 2021
Abstract- Memory has proven a major bottleneck in the development of energy-efficient chips for IoT applications and artificial intelligence (AI). Recent nonvolatile memory (NVM) devices not only serve as nonvolatile memory macros, but also enable the development of nonvolatile logics (nvLogics) for nonvolatile processors as well as computing-in-memory (CIM) for AI chips. In this tutorial, we begin with an introduction to various NVM technologies (i.e. MRAM, PCM, ReRAM) and the fundamental circuits used in NVM macros. We then review various state-of-the-art circuit techniques for low-power, high-speed on-chip NVM macros. In the third part of the tutorial, we examine some of the challenges involved in the further development of these technologies and review examples of NVM enabled nvLogics (i.e. nvFlipflop, nvSRAM, nvTCAM) for nonvolatile processors and CIMs for AI chips. Bio - Professor Chang received his M.S. from Pennsylvania State University and his Ph.D. degree from National Chiao Tung University in Taiwan. He is currently a full Professor at National Tsing Hua University, Taiwan. Before 2006, he has worked in industry over 10 years.
Between 1997 and 2006, Dr. Chang worked in the design of circuits for SRAM/Flash compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and IPLib (Taiwan). His research interests include circuit design for volatile and nonvolatile memory, in-memory-computing, artificial intelligence chips, and neuromorphic computing.
Since 2010, Professor Chang has co-authored 35+ top-tier conference papers (14 ISSCC, 14 VLSI, 8 IEDM, and 4 DAC), 30+ IEEE journal papers, and 40+ granted US patents. He is an associate editor for IEEE TVLSI, IEEE TCAD, and IEICE Electronics, and has been serving on the TPC for ISSCC, IEDM (Chair of Memory Technology for 2017), A-SSCC, IEEE CAS Society (Chair Elect of NG-TC), and numerous conferences. He has also been serving as the Associate Executive Director for Taiwan’s National Program of Intelligent Electronics (NPIE) since 2011.
Between 1997 and 2006, Dr. Chang worked in the design of circuits for SRAM/Flash compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and IPLib (Taiwan). His research interests include circuit design for volatile and nonvolatile memory, in-memory-computing, artificial intelligence chips, and neuromorphic computing.
Since 2010, Professor Chang has co-authored 35+ top-tier conference papers (14 ISSCC, 14 VLSI, 8 IEDM, and 4 DAC), 30+ IEEE journal papers, and 40+ granted US patents. He is an associate editor for IEEE TVLSI, IEEE TCAD, and IEICE Electronics, and has been serving on the TPC for ISSCC, IEDM (Chair of Memory Technology for 2017), A-SSCC, IEEE CAS Society (Chair Elect of NG-TC), and numerous conferences. He has also been serving as the Associate Executive Director for Taiwan’s National Program of Intelligent Electronics (NPIE) since 2011.
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