Device and Physical Design Considerations for Circuits in FinFET Technology Slides and Transcript

Abstract: CMOS scaling remains economically lucrative with 7nm mobile SoCs commercialized since late 2018 and 5nm products imminently available. Modest feature-size reduction and process innovations optimized for logic and SRAM scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. This talk provides an overview of the key process technology elements that have enabled the FinFET CMOS nodes and highlights the resulting technology impact on design. Bio: Alvin Loke is a Director in the TSMC San Diego Design Center focusing on analog design methodologies and technology co-optimization in advanced CMOS. He received his PhD from Stanford in 1999, spent several years in CMOS process integration, and worked on wireline/clocking design and design/technology interface at Agilent, AMD, and Qualcomm. Alvin has authored over 50 publications and 28 patents. He is currently a VLSI Symposia TPC member, SSCS Webinar Coordinator for North America, and San Diego SSCS Chapter Chair. He previously served as a Distinguished Lecturer, CICC TPC member, and JSSC and SSCL Guest Editor. Alvin is recipient of the Canadian NSERC 1967 Scholarship, 2005 SSCS Outstanding Chapter Award, and CICC 2018 Best Paper Award.