ABSTRACT Despite the many applications that could substantially benefit from the energy-performance achievable with an SoC implemented in an advanced process technology, the high costs of designing and verifying such an SoC using current methodologies limits their adoption to end markets greater than $1B in size. Not only has this prevented substantial hardware innovation in emerging markets, but even in markets large enough to bear the high initial design cost, designers are being put under constant pressure to improve their productivity given increasingly tight time-to-market constraints and product cycles. In this talk, I will describe a collaborative effort to develop an agile approach that aims to substantially reduce the design and verification costs of such advanced SoCs. Building on principles originally developed for agile software design, the key missing piece for hardware is that rather than focusing on developing instances, designers should focus on developing generators that facilitate re-use and enable agile validation as well as verification. As I will describe in this talk, to support this shift in approach, our team is developing technologies that enable generation of digital and analog hardware as well as the means to verify the hardware that is produced. After briefly describing each of these technologies and highlighting some of their key features, I will then briefly describe the SoC generator we have developed and used to tape-out multiple SoC demonstrators on TSMCs 16nm FFC process.