IEEE Solid-State Circuits Directions Series: Think Impact with ICs: Solid State Circuits and Devices in Extreme Radiation Environments Video

Abstract: This workshop on Solid State Circuits and Devices in Radiation Environments explores the challenges and design techniques for developing reliable semiconductor components and integrated circuits for harsh radiation conditions, such as those encountered in space, nuclear, and high-energy physics environments. Participants will gain in-depth insights into the basics and latest advancements in radiation-hardened design approaches and technologies, with a focus on several key topics: 1. Radiation Effects on semiconductors components, Soumyajit Mandal Abstract: This talk will introduce the main effects of high-energy radiation on semiconductor detectors and integrated circuits. Broadly speaking, these effects can be categorized into stochastic and cumulative damage mechanisms. The former are typically caused by individual ionizing particles and are thus known as single event effects (SEEs), while the latter are functions of both the total ionizing dose (TID) received by the chip and the accumulation of displacement damage within the semiconductor lattice. The occurrence and properties of radiation-induced damage will be discussed in the context of the radiation environments experienced by electronics in three important applications, namely space missions, nuclear reactors, and particle accelerators. The impact of process scaling and prospects for the future will also be presented. 2. Radiation Hardening By Design (RHBD) in CMOS standard process, Cristiano Calligaro Abstract: In this talk an overiview on the most common techniques for radiation hardening by design (RHBD) will be discussed with a specific focus on standard CMOS process available in nodes from 250nm down to 28nm. Both TID and SEE mitigation strategies at architecture, circuit and layout level will be described showing practical examples in standard cells, SRAMs and analog devices (e.g. data converters). 3. On-Chip Infrastructure for Mission-Mode Monitoring of Resilient Systems: Towards Silicon Lifecycle Management, Fabian Vargas Abstract: Simulation and laboratory measurements can never tell the whole story of how devices will behave in real-world use. In real world, various interferences can occur simultaneously, where the IC can be exposed, for instance, to extreme environmental temperatures, battery wear-out/instability, electromagnetic interference (EMI), ionizing radiation (TID, SEEs) and aging (BTI, HCI, TDDB, electromigration). Moreover, there are many standards used to certify electronic circuits & systems, but they are applied independently (on fresh devices), not considering the combined effects one phenomenon may take over the other. In this always-challenging context, this talk gives us an insight on how IHP addresses the design of ICs through the use of on-chip cross-layer infrastructure, and how we can enable a range of new (in-field) optimizations throughout the lifecycle of the circuits. Such infrastructure deals with sensors to detect SEU in memory elements and SET in logic, monitoring power-supply activity, temperature, measuring electronics aging and tracking in-field real-time circuit speed performance degradation during IC lifetime. Other types of monitors (watch-dogs) aim to guarantee mixed-criticality task execution in real-time operating system (RTOS). Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std. This on-chip infrastructure is being implemented in different versions of a RISC-V processor, and manufactured with the IHP’s BiCMOS 130nm rad-hard technology. This solution enables mission-mode monitoring of IC operation, which is a critical aspect of silicon lifecycle management (SLM) framework. 4. Matrix Radiation Sensors in a standard CMOS technology, Yakov Roizin Abstract: Ionizing radiation sensing devices based on the floating gate (FG) principle and methods of their operation are discussed in the talk. The focus is on the novel sensors comprising two identical arrays of single Poly FG cells with integrated low-capacitance ionization chambers, where each cell in one array has a counterpart in the other array. The cells from two arrays are connected into logical diferential pairs. The device is programmed before sensing and does not need a power supply in the registation mode. For ultra-low dose measurements or registration of single effects, the number of logical pairs influenced by radiation is evaluated. Special algorithms are used to mitigate the influence of retention effects, read disturbs and noises of the single cells. For large doses, the mean threshold voltage shifts are used as a measure of the absorbed dose. The exemplary 256×256 array prototypes fabricated in a standard 180nm 5V CMOS flow (die size 6.5mm x 6.5mm) allowed detectable doses of gamma and X-ray radiation down to 100 microGray. 5. Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments, Philip Neudeck Abstract: This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1,2], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [3], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [4]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages [5]. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, the majority of processing steps necessary to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment. 6. ESA programs and standards for ASIC, FPGA and IP Cores for space, Agustín Fernández León Abstract: ESA has recently led a major update of the ECSS standard applied for the development of ASIC, FPGA and IP Cores that are used in ESA spacecraft. Two new complementary standards, one centred in engineering requirements and second one addressing product assurance were as a result published in October of 2023 and are since then applicable. I will walk the audience through the main contents and requirements laid our in the engineering standard- This standard makes reference to an ECSS handbook available since 2016 that explains a large number of techniques that can be applied, at various levels of the IC development, to mitigate the effects of radiation on ICs. A brief walk through this handbook will also be presented. Lastly, I will conclude with a short summary of the most recent developments that ESA is engaged in in order to make the next generations of radiation hardened ultra-deep submicron (28, 22 and 7 nm ) technology and European devices available.