Design Techniques for Scalable, Sub-pJ/b Serial I/O Transceivers Video

13 Sep 2018
Samuel Palmero
Video Length / Slide Count:
Time: 01:18:21
Abstract In order to meet the inter chip bandwidth demands of future systems and comply with limited IC power budgets, both chip to chip data rates and IO energy efficiency must improve. This is a significant challenge for electrical interconnect architectures, which currently offer the lowest cost solutions, as the frequency dependent loss of conventional electrical channels prohibit significant data rate scaling without efficient equalizer circuits. This talk will discuss key design techniques that enable scalable, low power serial IO transceivers. The first part of the talk will discuss low power transmitter and receiver designs capable of low voltage operation and fast power state transitioning. Next, low complexity clocking architectures are detailed. The talk concludes with a discussion on low power equalizer circuits that enable the support of higher data rates over lossy channels. Speaker Biography Samuel Palermo received the B.S. and M.S. degrees in electrical engineering from Texas A and M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed signal integrated circuits for high speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high speed optical and electrical IO architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A and M University where he is currently an associate professor. His research interests include high speed electrical and optical interconnect architectures, RF photonics, high performance clocking circuits, and integrated sensor systems. Dr. Palermo is a recipient of a 2013 NSF CAREER award. He is a member of Eta Kappa Nu and IEEE. He is currently an associate editor for IEEE Solid State Circuits Letters and has previously served as an associate editor for IEEE Transactions on Circuits and Systems II from 2011 to 2015. He has also served on the IEEE CASS Board of Governors from 2011 to 2012. He is currently a distinguished lecturer for the IEEE Solid State Circuits Society. He was a coauthor of the Jack Raper Award for Outstanding Technology Directions Paper at the 2009 International Solid State Circuits Conference, the Best Student Paper at the 2014 Midwest Symposium on Circuits and Systems, and the Best Student Paper at the 2016 Dallas Circuits and Systems Conference. He received the Texas A and M University Department of Electrical and Computer Engineering Outstanding Professor Award in 2014 and the Engineering Faculty Fellow Award in 2015.