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12 Nov 2018
Abstract
In this short talk, the fundamental concepts of mmWave phased-array transceivers for 5G applications are introduced. Considerations of path-loss at mmWave are presented. The basic principles of beamforming and beamsteering for phased-arrays are shown. The talk concludes with link budget considerations for phased-array systems and high-level trade-offs for few transceiver architectures that implement beamforming, in terms of power consumption, area, linearity and general capabilities.
Biography
Stefano Pellerano is a principal engineer at Intel Labs, leading the Next Generation Radio Integration Lab. He drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies.
Since joining Intel Labs in 2004, Stefano worked on MIMO transceivers for WiFi, digital PLLs, high-efficient digital architectures for polar and outphasing transmitters, mm-wave radio transceiver and phased-array systems, and low-power radios. His latest research interests also include cryogenic CMOS integrated electronics for qubit control in fault tolerant scalable quantum computers.
Before joining Intel, Stefano got his Laurea and PhD degrees from Politecnico di Milano, Italy, in 2000 and 2004 respectively, after an internship in 2003 with Agere System (former Bell Labs) in Allentown, PA. His PhD thesis focused on the design of fully-integrated low-power frequency synthesizers for WLAN applications.
Stefano has authored or co-authored more than 40 IEEE conference and journal papers, one book chapter and more than 15 issued patents. He is currently the Wireless Subcommittee Chair of the International Solid-State Circuit Conference (ISSCC) and the TPC Chair of the Radio Frequency Integrated Circuit (RFIC) Symposium for 2018.
In this short talk, the fundamental concepts of mmWave phased-array transceivers for 5G applications are introduced. Considerations of path-loss at mmWave are presented. The basic principles of beamforming and beamsteering for phased-arrays are shown. The talk concludes with link budget considerations for phased-array systems and high-level trade-offs for few transceiver architectures that implement beamforming, in terms of power consumption, area, linearity and general capabilities.
Biography
Stefano Pellerano is a principal engineer at Intel Labs, leading the Next Generation Radio Integration Lab. He drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies.
Since joining Intel Labs in 2004, Stefano worked on MIMO transceivers for WiFi, digital PLLs, high-efficient digital architectures for polar and outphasing transmitters, mm-wave radio transceiver and phased-array systems, and low-power radios. His latest research interests also include cryogenic CMOS integrated electronics for qubit control in fault tolerant scalable quantum computers.
Before joining Intel, Stefano got his Laurea and PhD degrees from Politecnico di Milano, Italy, in 2000 and 2004 respectively, after an internship in 2003 with Agere System (former Bell Labs) in Allentown, PA. His PhD thesis focused on the design of fully-integrated low-power frequency synthesizers for WLAN applications.
Stefano has authored or co-authored more than 40 IEEE conference and journal papers, one book chapter and more than 15 issued patents. He is currently the Wireless Subcommittee Chair of the International Solid-State Circuit Conference (ISSCC) and the TPC Chair of the Radio Frequency Integrated Circuit (RFIC) Symposium for 2018.
