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12 Nov 2018
Abstract
This talk overviews on basic pixel structure of CMOS image sensors (CIS), including 3-transistor and 4-transistor pixels, pixel share structure and a global shutter pixel, and basics of signal chain from pixel to column parallel ADC through column circuits. It also introduces cross section of BSI pixel structure with aggressive stacking with 3-layer stacking. Then this talk covers how circuits can contribute to improve the performance of CMOS image sensors to improve dynamic range, and frame rates. Pixel parallel ADC is introduced as the pioneering work, and now in reality as stacked BSI structure. Frequency conversion technique is introduced as an example of time-domain signal processing to expand dynamic range. And further time stamping technique is introduced for both expanding the dynamic range, as well as for in-pixel gamma correction. Finally, ultra-high speed image sensor is introduced, which enables more than 1Mfps by utilizing high speed column parallel ADC and in-column analog memories.
Speaker Biography
Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a
research associate, in 1996, and now professor at the department of electrical engineering and information systems. At the same time he has been involving the activities of VDEC(VLSI Design and
Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia.
He worked for smart image sensor for 3-D range finding,time-domain circuits for associate memories, asynchronous circuits design, and hardware security including encryption engine design. He has
published more than 230 technical publications, including 10 invited papers, and 7 books/chapters. He is a senior member of IEEE, IEICE and member of IPSJ and ACM. He served number of positions in
international conferences, including ISSCC IMMD sub-committee chair for ISSCC 2015-2018, A-SSCC 2015 Program Committee Chair, VLSI Circuits Symposium Program Committee Chair for VLSI 2016 and
2017 and Symposium chair for VLSI 2018 and 2019.
This talk overviews on basic pixel structure of CMOS image sensors (CIS), including 3-transistor and 4-transistor pixels, pixel share structure and a global shutter pixel, and basics of signal chain from pixel to column parallel ADC through column circuits. It also introduces cross section of BSI pixel structure with aggressive stacking with 3-layer stacking. Then this talk covers how circuits can contribute to improve the performance of CMOS image sensors to improve dynamic range, and frame rates. Pixel parallel ADC is introduced as the pioneering work, and now in reality as stacked BSI structure. Frequency conversion technique is introduced as an example of time-domain signal processing to expand dynamic range. And further time stamping technique is introduced for both expanding the dynamic range, as well as for in-pixel gamma correction. Finally, ultra-high speed image sensor is introduced, which enables more than 1Mfps by utilizing high speed column parallel ADC and in-column analog memories.
Speaker Biography
Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a
research associate, in 1996, and now professor at the department of electrical engineering and information systems. At the same time he has been involving the activities of VDEC(VLSI Design and
Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia.
He worked for smart image sensor for 3-D range finding,time-domain circuits for associate memories, asynchronous circuits design, and hardware security including encryption engine design. He has
published more than 230 technical publications, including 10 invited papers, and 7 books/chapters. He is a senior member of IEEE, IEICE and member of IPSJ and ACM. He served number of positions in
international conferences, including ISSCC IMMD sub-committee chair for ISSCC 2015-2018, A-SSCC 2015 Program Committee Chair, VLSI Circuits Symposium Program Committee Chair for VLSI 2016 and
2017 and Symposium chair for VLSI 2018 and 2019.
