SoC Design Methodology for Improved Robustness Video

Posted: 17 Feb 2013

Authors:

Anthony Hill

Time:01:19:08

Tags :

Pricing:

SSCS Members: Free

IEEE Members: $25.00

Non-members: $40.00

Please sign in at the top of the page. If you are not an IEEE member, please create a free account to make a purchase or become a society member to have access to all materials for free.

Recent Items

Low-EVM High-Bandwidth Efficient CMOS RF-Transmitters Video

Low-EVM High-Bandwidth Efficient CMOS RF-Transmitters Slides

Trends in Broadband Converters Video

Trends in Broadband Converters Slides

Nonvolatile Spintronic Memory Array Performance Benchmarking Based on Three-Terminal Memory Cell

Enabling and Exploiting Machine Learning in Ultra-low-power Devices Video

Enabling and Exploiting Machine Learning in Ultra-low-power Devices Slides

Compact Modeling of Distributed Effects in 2-D Vertical Tunnel FETs and Their Impact on DC and RF Performances

Evaluating Spintronic Devices Using the Modular Approach

Nonboolean Pattern Recognition Using Chains of Coupled CMOS Oscillators as Discriminant Circuits

Solid-State Circuits Society
Resource Center

Short Courses and Tutorials Home

Webinars Home

VLSIx Home

Publications Home