Chip-to-Chip Wireline Communication Slides
Frank O'Mahony
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IEEE Members: Free
Non-members: FreePages/Slides: 19
12 Nov 2018
Abstract
This presentation is an introduction to chip-to-chip wireline communication. It starts by discussing how wireline links, or SerDes, are used within data center and supercomputer applications. It summarizes the data rate scaling trend for several SerDes industry standards and explains why per-lane data rates have scaled exponentially over the past two decades. Next it introduces the concept of channel characteristics in the frequency and time domains and provides an overview of common SerDes link architectures focusing on equalization techniques. It discusses the primary tradeoffs for scaling data rate, including interconnect distance, channel loss and power. The presentation then introduces several emerging trends in SerDes architecture, including PAM-4 modulation and analog-to-digital converter (ADC)-based receivers. It concludes by providing examples of SerDes transceivers from ISSCC 2018 that cover a range of data rates (up to 112Gb s), interconnect reach and architectures.
Speaker Biography
Frank currently leads the I O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Senior Principal Engineer. His group develops the first wireline I O circuits for each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel�s Circuit Research Lab. His research interests include high-speed and low-power transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank is currently the chair of the ISSCC Wireline Subcommittee and previously served as an Associate Editor for TCAS-I. Since 2003 he has published over 40 papers in peer-reviewed conferences and journals on the topic of wireline transceivers and clocking. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. He has also served as an IEEE Distinguished Lecturer.
This presentation is an introduction to chip-to-chip wireline communication. It starts by discussing how wireline links, or SerDes, are used within data center and supercomputer applications. It summarizes the data rate scaling trend for several SerDes industry standards and explains why per-lane data rates have scaled exponentially over the past two decades. Next it introduces the concept of channel characteristics in the frequency and time domains and provides an overview of common SerDes link architectures focusing on equalization techniques. It discusses the primary tradeoffs for scaling data rate, including interconnect distance, channel loss and power. The presentation then introduces several emerging trends in SerDes architecture, including PAM-4 modulation and analog-to-digital converter (ADC)-based receivers. It concludes by providing examples of SerDes transceivers from ISSCC 2018 that cover a range of data rates (up to 112Gb s), interconnect reach and architectures.
Speaker Biography
Frank currently leads the I O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Senior Principal Engineer. His group develops the first wireline I O circuits for each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel�s Circuit Research Lab. His research interests include high-speed and low-power transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank is currently the chair of the ISSCC Wireline Subcommittee and previously served as an Associate Editor for TCAS-I. Since 2003 he has published over 40 papers in peer-reviewed conferences and journals on the topic of wireline transceivers and clocking. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. He has also served as an IEEE Distinguished Lecturer.
